Export
You can export individual modules for functional verification.
You can also export the entire CSL design for both functional
and timing simulation.
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Waveform
You can choose VHDL or Verilog simulation netlist.
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FDL
FastChip's Device Link Utility allows you to instantly
download your design to a CSoC and debug your design.
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GDB
In addition to FDL, you can use 3rd party IDE to do simultaneous
hardware/software co-debug not found in any other SOC design.
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Tracedump
You can set up complex trace conditions in the FastChip Device
Link and view the on-chip trace buffer's content.
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